Layers are often formed over semiconductor substrates, e.g., wafers, during semiconductor device fabrication. Among the materials which may be included in such layers are tantalum pentoxide, titanium nitride, titanium silicon nitride, tantalum nitride, tantalum silicon nitride, titanium silicide, tantalum silicide, tungsten nitride, aluminum oxide, hafnium oxide, zirconium oxide, silicon nitride, silicon dioxide, elemental tungsten and elemental titanium. Example methods for forming such layers are chemical vapor deposition (CVD) and atomic layer deposition (ALD).
CVD includes mixing two or more reactants in a chamber to form a material which subsequently deposits across exposed surfaces of a substrate. In CVD processes, it may be difficult to control reactions between the reactants provided in the chamber, and various side reactions may occur. The side reactions may generate contaminants. Additionally, it may be difficult to form a uniform layer over multiple exposed surfaces of one or more substrates with CVD. For instance, chemical vapor deposition of material may be faster across some regions of semiconductor topography relative to others, which may lead to within wafer (WIW) non-uniformity.
ALD may overcome some of the problems discussed above relative to CVD. ALD processing includes forming thin films of material by repeatedly depositing monoatomic layers.
ALD processes may involve introduction of a first reactant which reacts with a substrate to form a monolayer across the substrate. The first reactant may react with the substrate, but not with itself. Accordingly, side-reactions may be reduced or eliminated. Further, the reaction of the reactant with the substrate can be self-limiting. Thus, once a monolayer forms across exposed surfaces of the substrate there may be no further reaction of the reactant with the substrate.
In ALD processes, after the monolayer is formed, the excess first reactant may be evacuated from the reaction chamber via a purge process, and a second reactant may be subsequently introduced. A purge process may include one or more purge steps in which a purge gas is introduced into the reaction chamber. A purge process may also include one or more pumping steps preceding and/or following introduction of the purge gas to remove excess reactant, catalyst, purge gas, and/or by-product gases from the chamber.
In ALD processes, the second reactant may react with the monolayer of material formed from the first reactant to convert such monolayer into a desired material layer over the substrate. The desired material layer may have a relatively uniform thickness across the various surfaces of the substrate.
Depending on the reactant system and with long enough pump and/or purge time, an ALD process may produce very uniform thickness across a wafer regardless of topography. However, ALD processing may have significantly lower throughput as compared to CVD processing techniques. To improve the throughput associated with ALD processes, the purge process may be shortened by using shorter pump and/or purge times between reactant pulses. In some cases, the deposition rate associated with ALD processing may be improved by increasing or decreasing the process temperature. Also, ALD throughput may be improved by processing a plurality of wafers simultaneously in a batch process.
Performing batch processes, increasing or decreasing the process temperature, and/or shortening pump and/or purge times may, however, lead to an added CVD component associated with an ALD process (in other words, may lead to the process being a mixed ALD/CVD process). A process which is primarily ALD, but which has some CVD occurring therein, may be referred to as a quasi-ALD process. The CVD process characteristics of a quasi-ALD process may increase throughput of the process, but may also lead to problems with WIW uniformity.
A prior problem may be that the wafers being treated by a quasi-ALD process need a long time to stabilize to a process temperature (especially at lower temperatures, such as temperatures of from 75° C. to 125° C.), and yet it is important to avoid overshooting a target temperature (as overshoot may damage structures or materials on the wafers). Thus, slow, controlled heating is utilized. If deposition is started at a lower temperature, the CVD component may lead to a thickness profile of the type shown in FIG. 1. Specifically, FIG. 1 shows a construction 10 illustrating a thickness profile of a material 14 formed on a semiconductor substrate 12 utilizing prior art quasi-ALD processing.
Material 14 may comprise any material that can be deposited by an ALD process, and may, for example, correspond to an oxide, such as Al2O3, TiO2, ZrO2, HFO2, Ta2O5, Nb2O5, CeO2, SiO2, In2O3, or IrO2; a nitride; a metal or a silicide. For instance, material 14 may comprise silicon dioxide formed by ALD utilizing a silicon-containing precursor (for instance, Si2Cl6), an oxygen-contain precursor (for instance, H2O), and a pyridene catalyst.
The substrate 12 has an inner (or central) region 5, and outer regions laterally outward from such inner region. The inner and outer regions are defined by their relative location to one another on substrate 12, and not by discrete physical differences in composition that may or may not exist between the inner and outer regions.
The material 14 has a non-uniform thickness profile, and specifically is thicker over the outer regions 7 of substrate 12 than over the inner region 5 of such substrate. The difference between the maximum and minimum thicknesses of layer 14 (in other words, the thickness variance) may be used as a measure of WIW uniformity. The thickness variance is indicated in FIG. 1 by a distance 15.
The WIW uniformity of a layer may be determined based on a measured thickness of the layer at a number of different points across a semiconductor substrate. The WIW uniformity may be proportional to the difference between a maximum thickness measurement and a minimum thickness measurement. Under such definition, WIW uniformity measurements closer to zero indicate a layer having a more uniform thickness profile.
It is desired to develop methods for improving WIW uniformity, while also achieving high throughput of deposition processes.